The present technique relates to an apparatus and method for controlling access to a memory device.
Typically, a memory controller will be provided for a memory device, the memory controller being arranged to receive access requests from one or more requesting devices, and then to issue commands to the memory device to cause the accesses required by those access requests to be performed. The memory controller may be provided with a pending access requests storage in which access requests waiting to be issued to the memory device are temporarily stored. The memory controller can then seek to schedule the various access requests in the pending access requests storage so as to seek to optimise performance of the memory device.
In particular, many memory devices are arranged to consist of a plurality of sub-structures. The various sub-structures within the memory device will vary dependent on the type of memory device. As one particular example, considering a Dynamic Random Access Memory (DRAM) device, this is often organised into ranks, banks, rows and columns, and indeed at a higher hierarchical level there may be multiple channels. The access timing characteristics of the memory device may be such that there are certain access timing penalties associated with switching between the various sub-structures of the memory device, and accordingly the memory controller can try to re-order the access requests in the pending access requests storage so as to seek to reduce such timing penalties, and hence improve the overall memory performance.
However, within modern data processing systems, as the number of potential requesting devices communicating with the memory controller increases, the memory controller can become a performance bottleneck within the system. Further, whilst the memory controller can seek to re-order how the access requests within the pending access requests storage are performed, with the aim of improving performance, it only has the ability to re-order the access requests that are actually in the pending access requests storage, and the pending access requests storage has a finite size.
Accordingly, it would be desirable to provide a technique for increasing the efficiency of operation of a memory controller.